View AK7756VF_3671391.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

[ak7756] ms1218-e-00-pb 2010/08 1 the ak7756 is a highly integrated digital signal processor, including a mono voice audio codec, a mic pre-amplifier and digital audio i/f. the audio dsp has 9216step at fs = 8khz parallel processing power. as the ak7756 is a ram based dsp, it is programmab le for user requirements such as hands free and acoustic effect. the ak7756en is available in a space saving small 28pin qfn package and the AK7756VF is available in a 30pin vsop package. ? dsp - word length: 24bit (data ram 24bit floating point) - instruction cycle: 13.6 ns (9216 steps at fs=8 khz) - multiplier 20 x 20 36bit (double precision available) - divider 20 / 20 20bit - alu: 36bit arithmetic operation (with over flow margin 4bit) 24bit floating point arithmetic and logic operation - program ram: 3072 x 36bit - coefficient ram: 2048 x 20bit - data ram: 1024 x 24-bit (24bit floating point) - delay ram: 3072 x 20bit, 3072 x 20bit - master clock: 4.6mhz ~ 73.7mhz - jx pins (interrupt) ? audio serial i/f - master / slave operation - right / left justified and i 2 s - pcm (short / long frame) - 16bit linear, 8bit a-law, 8bit -law ? mono codec - sampling rate 8khz, 16khz - dac s/n: 91db, s/(n+d): 83db (fs:16khz) - adc s/n: 86db, s/(n+d): 77db (fs:16khz) ? microphone interface - differential or single-ended input - programmable gain (+33db ~ +15db and 0db, 3db step) - low noise microphone bias ? automatic power down (codec, dsp) ? p i/f : spi, i 2 c-slave ? i 2 c bootloader ? power supply analog (avdd) : 3.0v ~ 3.6v (typ.3.3v) digital1 (dvdd) : 3.0v ~ 3.6v (typ.3.3v) digital2 (dvdd18) : 1.7v ~ 1.9v (typ.1.8v) ? operating temperature range: -20 c ~ 85 c (ak7756en), -40 c ~ 85 c (AK7756VF) ? package: 28pin qfn (ak7756en) 30pin vsop (AK7756VF) general description features dsp with mono codec + mic/lineout am p ak7756
[ak7756] ms1218-e-00-pb 2010/08 2 block diagram akm dsp core p (i2c,spi)/ eeprom (i 2 c) interface sda/so eest/sdout3/si exteep/rqn i2csel memory line out pmdac din2 dout3 mic pmadc ain/inp inn d/a a/d dvdd18 vss1 dvdd vcom avdd vss2 mprf mic power supply pmmb micbias scl/sclk sto/rdy/sdout1 aout dout2 rdy irstn sdout2/rdy din1 dout1 i 2 s or pcm interface bick lrck sdin1 sdout1 wdt/ crc pll xti xto lflt seldo1 seldo2 osc pmosc jx1 jx1 jx0/sdin2 seldi2 seldo3 si eest i2csel pin jx0 jx0e jx1e figure 1. block diagram
[ak7756] ms1218-e-00-pb 2010/08 3 ordering guide ak7756en -20 +85 c 28pin qfn AK7756VF -40 +85 c 30pin vsop akd7756hfs evaluation board for ak7756 pin layout ak7756en mprf jx1 22 vcom 21 23 vss2 24 avd d 2 5 micbias 26 inp/ain 27 inn 28 a ou t 20 irstn 19 18 17 lrck 16 sdout2/rdy 15 lfl t 1 i2csel 2 xto 3 xti 4 dvdd18 5 6 dvdd 7 14 13 12 11 10 9 8 sto/rdy/sdout1 sda/so scl/sclk eest/sdout3/ si exteep/rqn jx0/sdin2 sdout1 top v ie w vss1 sdin1 bick
[ak7756] ms1218-e-00-pb 2010/08 4 AK7756VF 6 5 4 3 2 1 dvdd18 vss1 sdout1 jx0/sdin2 exteep/rqn 7 scl/sclk 8 xti xto i2csel lflt inn inp/ain micbias AK7756VF top view 10 9 sda/so st o/rdy/sdout1 sdout2/rdy 11 nc 12 avdd avdd vss2 vcom 25 26 27 28 29 30 24 23 21 22 20 19 eest/sdout3/si lrck 13 bick 14 mprf aout 18 17 sdin1 15 irstn 16 jx1 dvdd
[ak7756] ms1218-e-00-pb 2010/08 5 dsp block diagram cp0, cp1 cram 2048w x 20-bit dp0, dp1 dram 512w 24-bit mpx20 mpx20 ofreg 32w x 13-bit x y multiply 20 x 20 36-bit p i/f control pram 3072w x 36-bit dec pc stack: 5 level(max) mul dbus shift a b alu 40-bit overflow margin: 4-bit dr0 3 over flow data generator di vision 2 0 20 20 peak detector serial i/f cbus(20-bit) dbus(24-bit) 36-bit 24-bit 40-bit 40-bit 40-bit dlram 3072w x 20-bit ptmp(lifo) 6 x 24-bit dlp0, dlp1 1 x 24-bit 2 x 24-bit din1 din2 (adc or sdin2 pin) dlram address pointer 2 x 24-bit 40-bit dout1 tmp 12 x 24-bit 2 x 24-bit dout2 512w 24-bit 3072w x 20-bit 1 x 24-bit dout3 (dac or sdout3pin)
[ak7756] ms1218-e-00-pb 2010/08 6 pin/function (ak7756en) no. pin name i/o function 1 lflt o output pin for loop filter of pll circuit this pin must be connected to vss2 with 8.2k ? and 33nf in series. outputs ?l? during initial reset. 2 i2csel i p control mode select pin ?h?: i 2 c, ?l?: spi 3 xto o master clock output pin. outputs hi-z during initial reset. 4 xti i external master clock input pin 5 dvdd18 - digital power supply 2 pin. 1.7 1.9v 6 vss1 - ground pin 7 dvdd - digital power supply 1 pin. 3.0 3.6v 8 sdout1 o audio serial data output1 pin. outputs ?l? during initial reset. jx0 i conditional jump pin0 (jxoe bit = ?1?) 9 sdin2 i audio serial data input 2 pin (jxoe bit = ?0?) exteep i start to download from external eeprom (i2csel pin = ?h? : i 2 c bus mode) ?h?: start download (downl oad from external memory) ?l?: normal operation 10 rqn i p i/f write request pin (i2csel pin = ?l? : spi mode) when initial reset and p i/f are not in use, leave the rqn pin high level. eest o eeprom download busy output (i2csel pin = ?h? and seldo3 bit = ?0?) h: download is busy. l: download is complete. outputs ?l? during initial reset. sdout3 o audio serial data output pin3 (i2csel pin = ?h? and seldo3 bit = ?1?) outputs ?l? during initial reset. 11 si i control data input pin (i2csel pin = ?l?: spi mode) scl i control data clock pin (i2csel pin = ?h?: i 2 c bus mode) outputs hi-z during initial reset. 12 sclk i control data clock pin (i2csel pin = ?l?: spi mode) set this pin to ?h? when there are no clock inputs. sda i/o control data input /output pin (i2csel pin = ?h?: i 2 c bus mode) outputs hi-z during initial reset. 13 so o control data output pin (i2csel pin = ?l?: spi mode) outputs ?l? during initial reset. sto o status output pin rdy o data write ready output pin for p interface sdout1 o audio serial data output pin1 14 outputs ?h? during initial reset. sdout2 o audio serial data output2 pin rdy o data write ready output pin for p interface 15 outputs ?l? during initial reset. 16 lrck i/o audio channel select pin 17 bick i/o audio serial data clock pin 18 sdin1 i audio serial data input 1 pin 19 irstn i reset pin (active low) the ak7756 must be reset once upon power-up. ?h?: power-up, ?l?: initia lize the control register. 20 jx1 i conditional jump pin1 21 aout o analog output outputs. outputs vss2 during initial reset. 22 mprf o output pin for ripple filter of micbias circuit connect 1.0 f capacitor to vss2. outputs avdd during initial reset.
[ak7756] ms1218-e-00-pb 2010/08 7 23 vcom o analog common voltage output pin connect 0.1 f and 2.2 f capacitor to vss2. outputs vss2 during initial reset. 24 vss2 - ground pin 25 avdd - analog power supply pin 3.0 3.6v 26 micbias o microphone bias. outputs hi-z during initial reset. ain i single-ended analog input pin ( mdif bit = ?0?) 27 inp i positive microphone input pin ( mdif bit = ?1?) 28 inn i negative microphone input pin ( mdif bit = ?1?) note 1. all digital input pins must not be left floating. note 2. dvdd or vss1 voltage must be input to the i2csel pin. note 3. all analog input pins (inp/ain, inn pins) must be supplied signal via ac-coupling capacitor. note 4. analog output pins (aout pin) must deliver signal via ac-coupling capacitor pin/function (AK7756VF) no. pin name i/o function 1 dvdd18 - digital power supply 2 pin. 1.7 1.9v 2 vss1 - ground pin 3 dvdd - digital power supply 1 pin. 3.0 3.6v 4 sdout1 o audio serial data output1 pin. outputs ?l? during initial reset. jx0 i conditional jump pin0 (jxoe bit = ?1?) 5 sdin2 i audio serial data input 2 pin (jxoe bit = ?0?) exteep i start to download from external eeprom (i2csel pin = ?h? : i 2 c bus mode) ?h?: start download (downl oad from external memory) ?l?: normal operation 6 rqn i p i/f write request pin (i2csel pin = ?l? : spi mode) when initial reset and p i/f are not in use, leave the rqn pin high level. eest o eeprom download busy output (i2csel pin = ?h? and seldo3 bit = ?0?) h: download is busy. l: download is complete. outputs ?l? during initial reset. sdout3 o audio serial data output pin3 (i2csel pin = ?h? and seldo3 bit = ?1?) outputs ?l? during initial reset. 7 si i control data input pin (i2csel pin = ?l?: spi mode) scl i control data clock pin (i2csel pin = ?h?: i 2 c bus mode) outputs hi-z during initial reset. 8 sclk i control data clock pin (i2csel pin = ?l?: spi mode) set this pin to ?h? when there are no clock inputs. sda i/o control data input /output pin (i2csel pin = ?h?: i 2 c bus mode) outputs hi-z during initial reset. 9 so o control data output pin (i2csel pin = ?l?: spi mode) outputs ?l? during initial reset. sto o status output pin rdy o data write ready output pin for p interface sdout1 o audio serial data output pin1 10 outputs ?h? during initial reset. sdout2 o audio serial data output2 pin rdy o data write ready output pin for p interface. 11 outputs ?l? during initial reset. 12 nc - no connect pin. this pin must be connected to vss1.
[ak7756] ms1218-e-00-pb 2010/08 8 13 lrck i/o audio channel select pin 14 bick i/o audio serial data clock pin 15 sdin1 i audio serial data input 1 pin 16 irstn i reset pin (active low) the AK7756VF must be reset once upon power-up. ?h?: power-up, ?l?: initia lize the control register. 17 jx1 i conditional jump pin1 18 aout o analog output outputs. outputs vss2 during initial reset. 19 mprf o output pin for ripple filter of micbias circuit connect 1.0 f capacitor to vss2. outputs avdd during initial reset. 20 vcom o analog common voltage output pin connect 0.1 f and 2.2 f capacitor to vss2. outputs vss2 during initial reset. 21 vss2 - ground pin 22 avdd - analog power supply pin 3.0 3.6v 23 avdd - analog power supply pin 3.0 3.6v 24 micbias o microphone bias. outputs hi-z during initial reset. ain i single-ended analog input pin ( mdif bit = ?0?) 25 inp i positive microphone input pin ( mdif bit = ?1?) 26 inn i negative microphone input pin ( mdif bit = ?1?) 27 lflt o output pin for loop filter of pll circuit this pin must be connected to vss2 with 8.2k ? and 33nf in series. outputs ?l? during initial reset. 28 i2csel i p control mode select pin ?h?: i 2 c, ?l?: spi 29 xto o master clock output pin. outputs hi-z during initial reset. 30 xti i external master clock input pin note 1. all digital input pins must not be left floating. note 2. dvdd or vss1 voltage must be input to the i2csel pin. note 3. all analog input pins (inp/ain, inn pins) must be supplied signal via ac-coupling capacitor. note 4. analog output pins (aout pin) must deliver signal via ac-coupling capacitor handling of unused pin the unused i/o pins must be processed appropriately as below. classification pin name setting analog micbias, inp/ain, inn, aout, mprf these pins must be open. sdout1, sto/rdy/sdout1, sdout2/rdy, sdout3/eest/ si, xto these pins must be open. digital exteep/rqn, sdin1, xti, jx0/sdin2, jx1 these pins must be connected to vss1.
[ak7756] ms1218-e-00-pb 2010/08 9 absolute maximum ratings (vss1=vss2=0v; note 5 ) parameter symbol min max units power supplies: analog avdd ? 0.3 4.3 v digital 1 dvdd ? 0.3 4.3 v digital 2 dvdd18 ? 0.3 2.5 v difference(vss1~vss2) gnd -0.3 0.3 v input current, any pin except supplies iin - 10 ma analog input voltage ( note 6 ) vina ? 0.3 (avdd+0.3) or 4.3 v digital input voltage ( note 7 ) vind1 ? 0.3 (dvdd+0.3) or 4.3 v ak7756en ta ? 20 85 c ambient temperature (powered applied) AK7756VF ta ? 40 85 c storage temperature tstg ? 65 150 c note 5. all voltages with respect to ground. vss1 and vss2 must be the same voltage. note 6. inp/ain, inn pins note 7. irstn, i2csel, exteep, si/eest, sda/so, sc l/sclk, jx1, jx0, sdin1, lrck, and bick pins note 8.pull-up resistors at sda and scl pins must be connected to the dvdd voltage or less. do not turn off the power supplies when the sda and scl pins are pulled-up to dvdd. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1=vss2=0v; note 5 ) parameter symbol min typ max units power supplies analog avdd 3.0 3.3 3.6 v ( note 9 ) digital dvdd 3.0 3.3 3.6 v digital dvdd18 1.7 1.8 1.9 v difference1 avdd ? dvdd -0.3 0 +0.3 v note 5. all voltages with respect to ground. vss1 and vss2 must be the same voltage. note 9. the power-up sequence between avdd, dvdd and dvdd18 is not critical. but all power supplies must be on before starting operation of the ak7756. * akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[ak7756] ms1218-e-00-pb 2010/08 10 analog characteristics (codec) adc characteristics (ta=25oc; avdd=dvdd=3.3v, dvdd18=1.8v; vss1=vss2=0v; bick=64fs; signal frequency 1khz; measurement frequency =20hz~8 kh z, fs=16 khz, ckm mode 6, unless otherwise specified.) parameter min typ max units mic input programmable gain amplifier input resistance (inp, inn pins) (mgain = 0db) 22.5 30 37.5 k gain min (mgain2-0 bit = ?0h?) - 0 - db max (mgain2-0 bit = ?7h?) - +33 - db step size (mgain2-0bit = ?1h? ~ ?7h?) 3 db microphone bias supply: micbias pin bias output voltage ( note 10 ) 2.32 v load resistance 2.0 - - k load capacitance - - 30 pf resolution 24 bits dynamic characteristics ain pin mono adc sdout1 mgain=21db 72 db s/(n+d) (-1dbfs) mgain= 0db 69 77 mgain=21db 77 db dynamic range mgain= 0db 78 86 mgain=21db 77 db s/n mgain= 0db 78 86 microphone analog inputs inp,inn ( note 11 ) differential mgain= 0db 2.0 2.2 2.4 vpp mono adc full-scale input voltage single-ended mgain= 0db 2.0 2.2 2.4 vpp note 10. the output voltage is proportional to avdd. vmic bias=0.70 * avdd, iout=1ma note 11. the input voltage is proporti onal to avdd. vin=0.67 x avdd (typ.) @mgain = 0db
[ak7756] ms1218-e-00-pb 2010/08 11 dac characteristics (ta=25oc; avdd=dvdd=3.3v, dvdd18=1.8v; vss1=vss2=0v; bick=64fs; signal frequency 1 khz; measurement frequency=20hz~8 khz, fs=16 khz, ckm mode 6, unless otherwise specified.) parameter min typ max unit resolution 24 bits dynamic characteristics; mono dac aout pin s/(n+d) (0dbfs) 75 83 db s/n 83 91 db analog output full-scale output voltage ( note 12 ) 2.09 2.2 2.31 vpp load resistance 10 k ? mono dac load capacitance 30 pf note 12. full scale output voltage. the output voltage is proportional to avdd. vout=0.67 x avdd (typ.)
[ak7756] ms1218-e-00-pb 2010/08 12 (ta=tmin~tmax; avdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v; vss1=vss2=0v) parameter symbol min typ max unit high level input voltage ( note 13 ) vih 80%dvdd v low level input voltage ( note 13 ) vil 20%dvdd v scl, sda high level input voltage vih 70%dvdd v scl, sda low level input voltage vil 30%dvdd v high level output voltage: iout=-100 a ( note 14 ) voh dvdd-0.4 v low level output voltage: iout=100 a ( note 14 ) vol 0.4 v sda low level output voltage iout=3ma vol 0.4 v input leak current ( note 15 ) input leak current xti pin iin iix 26 10 a a note 13. except for the scl/sclk, sda/so pins. note 14. except for the sda/so pin. note 15. except for the xti pin. (ta=25oc; avdd=dvdd=3.3v; dvdd18=1.8v; vss1=vss2=0v, fin=1 khz, 24 bit, fs=8 khz (ckm mode = 0), dsps=bitfs=pmosc bits= ?0? pmmb bit= ?1?, dsp running with programmed connecting din2 with dout1 and din1 with dout3.) parameter min typ max units power supplies: ( note 16 ) power-up (irstn pin = ?h?) codec+dsp all circuit power-up avdd+dvdd 11.0 - ma dvdd18 avdd=dvdd=3.3v dvdd18=1.8v 6 - ma power consumption 47 mw avdd+dvdd 15 ma dvdd18 avdd=dvdd=3.6v dvdd18=1.9v 60 ma reset (irstn pin = ?l?), power-down condition ( note 17 , note 18 ) avdd+dvdd - 1 10 a dvdd18 3 200 a note 16. the consumption of dvdd18 depends on the master clock frequency and the step size of the dsp program. (bitfs bit = ?2h? and dsps bit = ?0?) note 17. all digital input pins are fixed to each supply pin (dvdd or vss1). note 18. the condition of maximum values specifies ta=tmin~tmax, avdd=dvdd=3.0~3.6v and dvdd18=1.7~1.9v. dc characteristics power consumption
[ak7756] ms1218-e-00-pb 2010/08 13 adc block 1. fs=8khz (ta= tmin~tmax, avdd= dvdd=3.0~3.6v, dvdd18=1.7~1.9v, vss1=vss2=0v; fs=8 khz) parameter symbol min typ max unit passband (0.1db) ( note 19 , note 20 ) (-0.02db) (-3.0db) pb 0 3.63 3.83 3.15 khz khz khz stopband sb 4.66 khz passband ripple ( note 20 ) pr 0.1 db stopband attenuation ( note 21 , note 22 ) sa 68 db group delay distortion gd 0 s group deley (ts=1/fs) gd 16 ts note 19. the characteristic of the high pass filter is not included. note 20. the passband is from dc to 3.15khz note 21. the stopband is 4.66khz to 507.34khz. note 22. the analog modulator samples the input signal at 512khz. 2. fs=16khz (ta= tmin~tmax, avdd= dvdd=3.0~3.6v, dvdd18=1.7~1.9v, vss1=vss2=0v; fs=16 khz) parameter symbol min typ max unit passband (0.1db) ( note 23, note 24) (-0.02db) (-3.0db) pb 0 7.26 7.66 6.3 khz khz khz stopband sb 9.32 khz passband ripple ( note 24 ) pr 0.1 db stopband attenuation ( note 25, note 26 ) sa 68 db group delay distortion gd 0 s group deley (ts=1/fs) gd 16 ts note 23. the characteristic of the high pass filter is not included. note 24. the passband is from dc to 6.3khz note 25. the stopband is 9.32khz to 1014.68khz. note 26. the analog modulator samples the input signal at 1024khz. digital filter characteristics
[ak7756] ms1218-e-00-pb 2010/08 14 dac block 1. fs=8khz (ta= tmin~tmax, avdd=dvdd= 3.0v ~ 3.6v, dvdd18= 1.7v ~ 1.9v; vss1=vss2=0v; fs=8 khz) parameter symbol min typ max unit passband (0.05db) ( note 27 ) (-6.0db) pb 0 4 3.62 khz khz stopband ( note 27 ) sb 4.37 khz passband ripple pr 0.01 db stopband attenuation sa 64 db group delay (ts=1/fs) ( note 28 ) gd 24 ts digital filter + analog filter amplitude characteristic 20hz~3.5khz 0.5 db note 27. pass band and stop band parameters are related to sampling frequency (fs). pb=0.4535fs (at-0.05db), sb=0.5465fs. note 28. the digital filter?s delay is calculated as the time from setting 16-bit data into the input register until an analog signal is output. 2. fs=16khz (ta= tmin~tmax, avdd=dvdd= 3.0v ~ 3.6v, dvdd18= 1.7v ~ 1.9v; vss1=vss2=0v; fs=16khz) parameter symbol min typ max unit passband (0.05db) ( note 27 ) (-6.0db) pb 0 8 7.24 khz khz stopband ( note 27 ) sb 8.74 khz passband ripple pr 0.01 db stopband attenuation sa 64 db group delay (ts=1/fs) ( note 28 ) gd 24 ts digital filter + analog filter amplitude characteristic 20hz~7.0khz 0.5 db
[ak7756] ms1218-e-00-pb 2010/08 15 system clock (ta= tmin~tmax, avdd=dvdd= 3.0v ~ 3.6v, dvdd18= 1.7v ~ 1.9v, vss1=vss2=0v, cl=20pf) parameter symbol min typ max unit master operation a) xti/xto with a x?tal, external clock input ckm[2:0]bits=6h(768x16khz) fxti 11.0 12.288 12.4 mhz duty cycle 40 50 60 % slave mode operation lrck frequency fs 8 16 khz bick frequency fbick 0.1 32fs/48fs/64fs 1.1 mhz duty 40 60 % reset (ta= tmin~tmax, avdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v; vss1=vss2=0v) parameter symbol min typ max unit reset pulse width ( note 29 ) trst 600 ns note 29. the irstn pin must be put to ?h? after all power supplies are powered up. switching characteristics
[ak7756] ms1218-e-00-pb 2010/08 16 digital audio interface (sdin1, sdout1, 2) 1) sdin1/2, sdout1/2/3 (ta= tmin~tmax, avdd=dvdd= 3.0v ~ 3.6v, dvdd18= 1.7v ~ 1.9v, vss1=vss2=0v, cl=20pf) parameter symbol min typ max unit i 2 s and pcm interface input timing delay time from bick ? ? to lrck ( note 30 ) tblrd 20 ns delay time from lrck to bick ? ? ( note 30) tlrbd 20 ns serial data input latch setup time tbsids 80 ns serial data input latch hold time tbsidh 80 ns delay time from lrck to serial data output ( note 31 ) tlrd 80 ns delay time from bick ? ? or ? ?to lrck output tbsod 80 ns i 2 s and pcm interface output timing sdout1/2 bick frequency bick duty cycle fbick 64 50 fs % delay time from bitclk ? ? to lrck output tmbl -20 40 ns serial data input latch setup time tbsids 80 ns serial data input latch hold time tbsidh 80 ns delay time from lrck to serial data output ( note 31 ) tlrd 80 ns delay time from bick ? ? or ? ?to lrck output tbsod 80 ns note 30. bick edge must not occur at the same time as lrck edge. note 31. except i 2 s.
[ak7756] ms1218-e-00-pb 2010/08 17 p interface (spi mode) (ta= tmin~tmax; avdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v, vss1=vss2=0v; cl=20pf) note 32. except when writing to the 8th bit of command code. p/eeprom interface (i 2 c bus mode) (ta= tmin~tmax; avdd=dvdd=3.0~3.6v, dvdd18=1.7~1.9v, vss1=vss2=0v; cl=20pf) parameter symbol min typ max unit i 2 c timing scl clock frequency fscl 400 khz bus free time between transmissions tbuf 1.3 s start condition hold time (prior to first clock pulse) thd:sta 0.6 s clock low time tlow 1.3 s clock high time thigh 0.6 s setup time for repeated start condition tsu:sta 0.6 s sda hold time from scl falling thd:dat 0 0.9 s sda setup time from scl rising tsu:dat 0.1 s rise time of both sda and scl lines tr 0.3 s fall time of both sda and scl lines tf 0.3 s setup time for stop condition tsu:sto 0.6 s pulse width of spike noise suppressed by input filter tsp 0 50 ns capacitive load on bus cb 400 pf note 33. i 2 c-bus is a trademark of nxp b.v. parameter symbol min typ max unit p interface timing (spi mode) rqn fall time twrf 30 ns rqn rise time twrr 30 ns sclk fall time tsf 30 ns sclk rise time tsr 30 ns sclk frequency fsclk 2.1 mhz sclk low level width tsclkl 200 ns sclk high level width tsclkh 200 ns rqn high level width twrqh 500 ns from rqn ? ? to irstn ? ? from irstn ? ? to rqn ? ? trst1 tirrq 600 100 ns s from rqn ? ? to sclk ? ? twsc 500 ns from sclk ? ? to rqn ? ? tscw 800 ns si latch setup time tsis 200 ns si latch hold time tsih 200 ns ak7756 p delay time from sclk ? ?to so output tsos 200 ns hold time from sclk ? ? to so output ( note 32 ) tsoh 200 ns
[ak7756] ms1218-e-00-pb 2010/08 18 timing diagram 1/fxti 1/fxti vih vil xti 1/fs 1/fs vih vil lrck tbickl tbickh 1/fbick 1/fbick vih vil bick tbick=1/fbick txti=1/fxti ts =1 / f s figure 2. system clock vil trst irstn figure 3. reset timing note 34. set the irstn pin = ?l? when power up and down the ak7756.
[ak7756] ms1218-e-00-pb 2010/08 19 tbsids tblrd tlrbd vih lrck bick vil vih vil vih vil tbsidh sdin1/2 figure 4. audio interf ace (slave mode input) tlr d vih lrck bick vil vih vil sdout1/2/3 tbsod tlr d tbsod 50%vdd figure 5. audio interface (slave mode output)
[ak7756] ms1218-e-00-pb 2010/08 20 figure 6. audio interface (master mode input) tlr d 50%dvdd lrck bick sdout1/2/3 50%dvdd tbsod tlrd tbso d 50%dvdd figure 7. audio interface (master mode output) tbsids tmbl tmbl 50%dvdd lrck bick vih vil tbsidh sdin1/2 50%dvdd
[ak7756] ms1218-e-00-pb 2010/08 21 tsclkh tsclkl 1/fsclk 1/fsclk trst1 tirrq rqn vih vil twrf twrr sclk vih vil tsf tsr irstn rqn vil vih vil vih figure 8. p interface 1 (spi ) twrqh tsis tsih tscw tscw twsc rqn si vih vil vih twsc sclk vil vih vil figure 9. p interface 2 (spi)
[ak7756] ms1218-e-00-pb 2010/08 22 tsos tsoh sclk vil vih so vih vil figure 10. p interface 3 (spi) thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 11. p interface (i 2 c bus)
[ak7756] ms1218-e-00-pb 2010/08 23 package (ak7756en) 28pin qfn (unit: mm) 5.00.07 5.00.07 b a 0.230.05 15 22 28 1 7 8 14 21 c0.30 0.05max 2.50 m 0.05 s a b 3.10 3.10 2.50 s 0.5 0.550.07 0.05 s 0.70 0.75max 0.00~0.05 0.18~0.28 0.12~0.18 [detail a] a note: the exposed pad on the bottom surface of the package must be open or connected to the ground. package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment : solder (pb free) plate
[ak7756] ms1218-e-00-pb 2010/08 24 package (AK7756VF) 30pin vsop (unit: mm) 1.200.10 0.10 +0.10 -0.05 1.50max 10.00max 0.17 +0.06 7.600.20 0.450.20 9.700.10 5.600.10 1 15 30 16 0.12 m 0.240.06 s 0.08 s 0~8 ? 0.65 0.30 -0.05 package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment : solder (pb free) plate
[ak7756] ms1218-e-00-pb 2010/08 25 marking (ak7756en) 7756 x xxx 1 xxxx : date code identifier (4 digits) marking (AK7756VF) akm AK7756VF xxxbyyyyc 1) akm logo 2) marketing code: AK7756VF 3) pin #1 identification 4) date code: xxxbyyyyc xxxb: lot number (x: digit number, b: alpha character) yyyyc: assembly date (y: dig it number, c: alpha character)
[ak7756] ms1218-e-00-pb 2010/08 26 date (yy/mm/dd) revision reason page contents 10/08/18 00 first edition important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these product s, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustra te the operation and application exam ples of the semiconductor products. you are fully responsible for the incorporation of these ex ternal circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these inform ation herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor auth orized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet ve ry high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medi cine, aerospace, nuclear energy, or ot her fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. revision history
[ak7756] ms1218-e-00-pb 2010/08 27 thank you for your access to akm products information. more detail product information is available, please contact our sales office or authorized distributors.

▲Up To Search▲

Price & Availability of AK7756VF

	To Download AK7756VF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .